Conventional power semiconductor devices, which have one or more power semiconductor chips, have electrical connecting elements which electrically connect top side and back side of the power semiconductor chip to external contact areas of the device. The external contact areas may be provided by a leadframe or on a wiring substrate. The electrical connecting elements may be provided by bonding wires, which extend between the top side of the power semiconductor chip and the external leads of the leadframe or through an electrically conducting clip from large-area electrodes of the top side of the semiconductor chip to the external contacts or the external leads, while a large-area backside electrode of the power semiconductor chip is fixed on a chip carrier of the leadframe.
Bonding wire connecting elements, as are used for a full-bridge circuit with power semiconductor components, are known from the document DE 196 35 582 C1. These have the disadvantage that they require a certain bonding loop height, with the result that the device package cannot be reduced in size any further. In order to overcome this problem, a planar wiring structure, which has at least two insulating films with conductor tracks, is to be provided, as known from document DE 10 2004 019 443 B3. One of the insulating films is laminated on the power semiconductor chip and has windows in which the conductor tracks of the other insulating film are to be arranged, in order to connect the contact areas of the power semiconductor chips electrically to a wiring substrate. However, this wiring solution has the disadvantage that the method of production is complicated, especially since a large number of components have to be produced, the components having to be adjusted to one another, laminated and mechanically and/or electrically connected to one another during production.